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High-Level Verification
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Pages: 176
Authors: Sudipta Kundu
Categories: Technology & Engineering
Type: BOOK - Published: 2011-05-18 - Publisher: Springer Science & Business Media

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Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly com
Verification Techniques for System-Level Design
Language: en
Pages: 251
Authors: Masahiro Fujita
Categories: Computers
Type: BOOK - Published: 2010-07-27 - Publisher: Morgan Kaufmann

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This book will explain how to verify SoC (Systems on Chip) logic designs using "formal and "semiformal verification techniques. The critical issue to be address
ASIC/SoC Functional Design Verification
Language: en
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Authors: Ashok B. Mehta
Categories: Technology & Engineering
Type: BOOK - Published: 2017-06-28 - Publisher: Springer

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This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environm
High-level Synthesis
Language: en
Pages: 334
Authors: Michael Fingeroff
Categories: Computers
Type: BOOK - Published: 2010 - Publisher: Xlibris Corporation

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Are you an RTL or system designer that is currently using, moving, or planning to move to an HLS design environment? Finally, a comprehensive guide for designin
Applied Formal Verification
Language: en
Pages: 259
Authors: Douglas L. Perry
Categories: Technology & Engineering
Type: BOOK - Published: 2005-05-10 - Publisher: McGraw Hill Professional

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Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how