Network on Chip Design for Heterogeneous Multicore Processors

Network on Chip Design for Heterogeneous Multicore Processors
Author :
Publisher :
Total Pages : 131
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ISBN-10 : OCLC:919287174
ISBN-13 :
Rating : 4/5 (74 Downloads)

Book Synopsis Network on Chip Design for Heterogeneous Multicore Processors by : Björn Striebing

Download or read book Network on Chip Design for Heterogeneous Multicore Processors written by Björn Striebing and published by . This book was released on 2015 with total page 131 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many embedded applications are heterogeneous in nature. They contain both, control and data driven elements. Such systems can be specified using the SystemJ programming language which follows the globally asynchronous locally synchronous formal model of computation. Control and data computations are separated and executed on two types of processor cores which are capable of handling these program parts efficiently. Hard real-time guarantees can be made by deriving worst case execution times to target safety critical systems. Static code analysis techniques for worst case execution time estimates not only rely on easily predictable timing models for processes cores. But in fact, upper bounds for communication delays between all cores are required. Concurrency can be increased and worst case execution times shortened, when multiple cores are combined into a heterogeneous multiprocessor platform. This thesis theoretically and practically investigates network on chip architectures with respect to their suitability for real-time applications, field-programmable gate array prototyping and scalability. It introduces a time division multiple access based multistage interconnect network for flexible and fast on chip interconnects. The resulting RT-HMP system is the first implementation of a real-time capable multicore processor supporting System J execution. Moreover, experimental validation over a range of benchmarks demonstrates the increased processing power, gained by employing multiple cores.


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