Download or read book Statistical Calibration for Two-step Analog-to-digital Conversion written by Yi-Long Yu and published by . This book was released on 2019 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes a two-step, hybrid and reconfigurable data converter using statistical calibration. The two-step analog-to-digital converter (ADC) has a front-end successive-approximation register (SAR) ADC and a back-end time-domain (TD) ADC, which together form a hybrid converter. An inter-stage sample-and-hold amplifier (SHA) doubles the operating speed by allowing the operation to be pipelined. A reconfigurable characteristic allows the converter resolution to be adjusted to be 8, 10 or 12 bits. Digital statistical calibration of ADCs can be implemented without any changes to the analog circuits, which allows it to be compatible with the characteristics of scaled CMOS, allowing potential savings in area and power dissipation. Unfortunately, statistical calibration requires some assumptions about the input density. However, these assumptions are less restrictive in this work than in previous work for two reasons. First, statistical calibration of the mismatch in the front-end capacitor arrays requires only that the input distribution be smooth (instead of requiring that the input be known as in previous work). Also, statistical calibration of inter-stage and back-end errors relies on the assumption that the residue or quantization error from the first stage is uniformly distributed. This residue characteristic holds for many ADC inputs and is intuitively explained in this thesis. To demonstrate the statistical calibration, a prototype ADC is fabricated in 40-nm CMOS technology. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration and 9.1 fJ per conversion-step including the estimated power dissipation for the calibration.