Compact Modeling and Simulation for Digital Circuit Aging
Author | : Jyothi Bhaskarr Velamala |
Publisher | : |
Total Pages | : 122 |
Release | : 2012 |
ISBN-10 | : OCLC:855220310 |
ISBN-13 | : |
Rating | : 4/5 (10 Downloads) |
Download or read book Compact Modeling and Simulation for Digital Circuit Aging written by Jyothi Bhaskarr Velamala and published by . This book was released on 2012 with total page 122 pages. Available in PDF, EPUB and Kindle. Book excerpt: Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and Dynamic Voltage Scaling (DVS) in real circuit operation. To overcome these barriers, the modeling effort in this work (1) practically explains the aging statistics due to randomness in number of traps with log(t) model, accurately predicting the mean and variance shift; (2) proposes cycle-to-cycle model (from the first-principle of trapping) to handle aging under multiple supply voltages, predicting the non-monotonic behavior under DVS (3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles, and (4) comprehensively validates the new set of aging models with 65nm statistical silicon data. Compared to previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard-banding during the design stage.