Download or read book Investigation of Degradation in Advanced Analog MOS Technologies written by Md. Iqbal Mahmud and published by . This book was released on 2014 with total page 169 pages. Available in PDF, EPUB and Kindle. Book excerpt: The focus of this work is to study the noise and degradation in advanced high and low voltage analog Metal Oxide Semiconductor Field Effect Transistors (MOSFET). Medium and high voltage transistors, especially lateral double diffused MOS (LDMOS) FETs are known as the workhorse for present day RF and analog mixed signal smart power applications. In presence of multiple in-plane Si-SiO2 interfaces in asymmetric LDMOS devives, additional defects are created in those interfaces. The trapping-detrapping in charge carriers by these traps lead to increased low frequency noise (LFN) degradation in LDMOS compared to CMOS transistors. Hence, LFN sets performance limit and increases the reliability concern in LDMOS devices. The majority of applications of LDMOS devices are in high frequency analog circuits and equipment, for example, in cellular communications, whereas 1/f noise is generally known to be important for frequencies up to 10 kHz. However, when the spectrum is up-converted to higher frequencies, noise gets amplified as well due to different nonlinearities in the system. This in effect, increases the phase noise in communication system and other reliability concerns during device operation. This can result in significant performance degradation of the system itself at the operational frequencies. This is why the study of 1/f noise degradation in medium and high voltage LDMOS is vital from the industry point of view. On the lower voltage side, analog submicron transistors are extensively utilized for obtaining high gain and bandwidth, while consuming low on-state power in analog to digital (and vice-versa) interfaces, in communication systems and in industrial electronics. Continuous downscaling of advanced submicron area low voltage analog MOSFETs requires rigorous in-depth study of the gate-oxide reliability. As compared to their high-voltage counterparts, these smaller devices have the oxide thickness of a few nanometers. This makes them vulnerable to individual defects in the Si-SiO2 interfaces more severely than the high-voltage devices. Hence, it is necessary to identify, quantify, individually characterize and accurately model electrically active defects (charge trapping and scattering centers) in scaled analog and mixed signal (AMS) devices. In this regard, random telegraph signal (RTS) noise measurement to characterize single charge carrier switching events in time domain, is of significant importance in present-day submicron device technologies, because of its versatility and inherent non-destructiveness to devices, as far as the device degradation is concerned. For LDMOS, the DC stress induced degradation characteristics of differently processed devices are studied in this work along with the noise performance. It is illustrated in this work that modeling the DC degradation alone cannot fully explain the physical mechanisms for LDMOS degradation. Hence, 1/f noise was utilized as a non-destructive characterization tool to quantitatively evaluate the device reliability and degradation at time-zero and after they were subjected to stress-induced degradation. Correlation has been established between low frequency noise and DC stress-induced degradation. From that, a simple but well-defined approach has been delineated to separate the indicidual resistance and noise coponents in different regions of these devices. The effect of extended drain drift region scaling on 1/f noise performance is studeies for different foundry-fabricated devices. An early lifetime prediction method for LDMOS is also reported here using 1/f noise measurements. This work represents the first ever physics-based 1/f noise model for LDMOS devices, and demonstrates that the developed model can correctly predict the experimentally observed noise behavior in the linear region of operation in fresh devices as well as in stressed devices. The model is based upon the correlation carrier number and mobility fluctuation theory known as the Unified 1/f Noise Model, but has been modified to account for the fluctuations in the extended drain as well as the channel. Unlike the Unified 1/f Noise Model, non-uniform trap distribution has been taken into account with respect to the position in the gate oxide and in the band-gap energy. In case of low voltage analog CMOS, we have demonstrated the RTS noise measurement and analysis technique to isolate each individual physical defect, and to characterize the trap properties both quantitatively and qualitatively. Multiple level RTS have been observed in submicron NMOS transistors at room temperature. From our analysis, we could ascertain the presence of two active traps, which are found to be responsible for four level RTS generation. Two different types of active traps- donor and acceptor, responsible for RTS generation, have been identified simultaneously for the first time in the same NMOS transistors at room temperature. A numerical computation method has been developed to separate fluctuations due to each trap, and to calculate the trap properties such as the mean capture and emission times, trap energy, capture cross-section and the distance into the oxide from the interface.