Download or read book Offset Calibration Techniques for High-speed CMOS Flash Analog-to-digital Converters written by Junjie Yao and published by . This book was released on 2010 with total page 188 pages. Available in PDF, EPUB and Kindle. Book excerpt: A 4-bit flash ADC with bulking voltage trimming technique was fabricated in 90 nm CMOS. The prototype occupies 0.135-mm2 active area. The ADC consumes 86 mW at 5 GS/s with an input of 2.5 GHz. The measured peak DNL and INL are 0.43 LSB and 0.37 LSB respectively for a 4-MHz input at 5 GS/s. The ADC achieves 3.71 ENOB at 5 GS/s with 2.5-GHz ERBW and a 1.32-pJ/convstep FOM. When operating at 6GS/s, the ENOB is 3.75 for a 4-MHz input and 3.10 for a-2 GHz input. Another 4-bit flash ADC with triode-load voltage trimming technique was designed in 65 nm CMOS. The active area is 0.0828mm 2 . The ADC consumes 34.3 mW at 5 GS/s with an input of 2.5 GHz. The measured DNL and INL after calibration are -0.44~0.41 LSB and -0.39~0.44 LSB respectively for a 4-MHz input at 5 GS/s. The ADC achieves 3.93 ENOB at 5 GS/s with 2.5-GHz ERBW and a 0.45-pJ/convstep FOM.